Because large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later.
Subscribe to:
Post Comments (Atom)
-
This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to... -
Static timing analysis verifies circuit timing by “ adding up propagation delays along paths between clocked elements ” in a circuit. It c...
-
Combinational loops are logical structures that contain no synchronous feedback element. This kind of loops cause stability and reliability ... -
Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered eve... -
Formal Definition An interface constant declared in the block header of a block statement, a component declaration, or an entity declaratio...
No comments:
Post a Comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.