Because large parts of the language make no sense in a hardware context, synthesizable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later.
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Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
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This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to...
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This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible comp...
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This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage. ...
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Formal Definition Comments provide a means of describing or documenting a model. Simplified Syntax // a single line with comments /* mult...
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Formal Definition Simulation control tasks allow you to stop or quit simulation. Simplified Syntax $ stop [(n)] ; $finish [(n)] ; Descri...
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