Fundamentally speaking, not a lot. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA. However, the two languages approach the task from different directions; VHDL, intended as a specification language, is very exact in its nature and hence very verbose. Verilog, intended as a simulation language, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modeling, whereas Verilog is much better than VHDL at gate-level simulation.
Featured post
Top 5 books to refer for a VHDL beginner
VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic des...
Subscribe to:
Post Comments (Atom)
-
This is in continuation of our previous post on Low Power Design Techniques , where we learned about different types of strategies used to...
-
Static timing analysis verifies circuit timing by “ adding up propagation delays along paths between clocked elements ” in a circuit. It c...
-
Combinational loops are logical structures that contain no synchronous feedback element. This kind of loops cause stability and reliability ...
-
Positive and negative edge detection is a common requirement in microprocessors. One application could be to detect edge/level triggered eve...
-
Formal Definition An interface constant declared in the block header of a block statement, a component declaration, or an entity declaratio...
No comments:
Post a Comment
Please provide valuable comments and suggestions for our motivation. Feel free to write down any query if you have regarding this post.