Top 5 books to refer for a VHDL beginner

VHDL (VHSIC-HDL, Very High-Speed Integrated Circuit Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and application-specific integrated circuits. To start with learning VHDL we are posting here the list of 5 VHDL books which are a good references to get started with VHDL coding.

1. VHDL: PROGRAMMING BY EXAMPLE - by Douglas L. Perry

 

  2. Digital Design | With an Introduction to the Verilog HDL, VHDL, and SystemVerilog - by M. Morris Mano

 

  3. A Vhdl Primer - by Bhasker

 

  

4. Fundamentals of Digital Logic with VHDL Design - by Stephen Brown and Zvonko Vranesic

 

 

5. Circuit Design and Simulation With VHDL - by Pedroni V.A

Please feel free to send your suggestions if there is any good book in your list. We will be happy to share here.

 

Effective VIM Editor tips, tricks and plugins to improve coding speed in VLSI

One of our colleagues always had to struggle with the Verilog / SystemVerilog syntax. Whenever he opens a .sv file he needs to set the syntax manually as ":set syntax=verilog". This really kills time, especially when you are working on a project with tight schedules. 

So today we are sharing a bunch of good tricks and different plugins that will help you code efficiently, whether Verilog, System Verilog, UVM or scripting languages like Perl. 

VIM editor is so powerful that everything can be modified using the keyboard. No need to raise a hand to reach out to the mouse. Thus the efficiency of working improves a lot and also looks more professional.

By default, vim invokes .vimrc every time a new file is opened. So we may configure any settings upfront in ~/.vimrc for making life easy while working with files.

We will start with basic keyboard shortcuts which will help us to work faster than the actual way.

Opening a fine using GVIM

To open any file from shell type :

gvim <filename>

By default, vim invokes .vimrc every time a new file is opened. So we may configure any settings upfront in ~/.vimrc for making life easy while working with files.

if you want to open multiple files in tab pages

gvim -p <filename1> <filename2> ..

if you want to open multiple files in horizontal windows

gvim -o <filenames>

if you want to open multiple files in vertical windows

gvim -O <filenames>

Shortcuts for moving the cursor:

h - move left

j - move down

k - move up

l - move right

Shortcuts for quick editing:

Letter level

r - quickly replaces the letter under the cursor.

i - change to insert mode. (ready for typing from before the cursor position) Esc to come out of insert mode.

I - change to insert mode at the start of a line.

a - change to append mode. (ready for typing after the cursor position), type ESC to come out of append mode.

A - change to append mode at the end of the line.

x - deletes the alphabet under the cursor and starts deleting the forward direction.

X - exactly like the backspace function.

o - change to insert mode on the next line.

O - change to insert mode on the previous line.

f - find a letter in the forward direction of a line.

F - find a letter in the backward direction of a line.

Word Level

w - move to the start of one word at a time.

      You can put any number upfront to move that many words

      Eg: 5w - From 1st word jumps to the start of 6th word.

b - move to the beginning of the word at a time.

e - move to the end of one word at a time.

y - yanks (that means you can copy a word till the end of a word, or a line, etc by using commands ye, yw, yy, etc)

p - paste whatever is yanked after the cursor

P - paste whatever is yanked before the cursor

d - deletes (that means you can delete a word till the end of a word, or a line, etc by using commands de, dw, dd, etc)

D - deletes from the cursor position to the end of the line.

0 - Go to the start of the Line.

Other General commands with keys

u - undo

gg - Go to the start of the file

G -  Go to the end of the file

ZZ - write, save and close the file

H - Head of the file in the visible pane

M - Middle of the file in the visible pane.

L - Last of the file in the visible pane.

v- enter visual mode from the alphabet under the cursor.

V - enter visual mode from the line under the cursor.

Advanced commands :

q - recording (will explain this in detail)

/ - search a word (eg : /<pattern>)

n- searches any word in forwarding direction

N - searches any word in the backward direction

. - repeats the last done job again.

? - for searching a word backward (more powerful than / )

Other General commands with additional keys

ctrl + e - scroll in forward direction

ctrl + p - scroll in backward direction

ctrl + r - redo

ctrl + a - increment the number in the line.

ctrl + x - decrement the number in the line.

ctrl + q or ctrl + v, enter visual mode in the column.

Shift + ~ - Invert the text case under the cursor

Vu  - if you want to convert the whole line of text under the  cursor to a Lowercase line

VU - if you want to convert the whole line of text under the  cursor to an Uppercase line

In gvim by typing ":" we enter into command line mode, we have a specific set of commands to use at this level.

How do I switch between panes in a split mode in Vim/GVIM ??

In command mode, hit Ctrl-W and then a direction, or just Ctrl-W again to switch between panes.

:b <number>  will open the specified buffer in the current pane.

Example  : UNIX > vim test_1 test_2 ; #  This command opens two test_1 and test_2 files

But in vim, we can see only one file(by default the first file test_1) with this approach.

If want to go to the test_2 file then use :b 2

:ls will show your open buffers

If we opened multiple vim files like above and want to know which are in buffer use this command

and with the help of :b <number>, we can switch between files

If we open many windows in vim/gvim  and you want to have equal window size for all split pans

Esc mode  Ctrl+W =

For more info type:

:help window-resize

you can use <ctrl> + w + w To switch the panes in order.

A suggested way is to put these codes in your vimrc file

map <C-j> <C-W>j

map <C-k> <C-W>k

map <C-h> <C-W>h

map <C-l> <C-W>l

How to remove blank lines from a file?

Here's a handy one-liner to remove blank lines from a file.

           :g/^$/d

Breaking this down. The "g" will execute a command on lines that match a regular expression.

The regular expression matches blank lines, and the command is "d" (delete).

You can also use

           :v/./d

(v means complementary, so any line that doesn’t have a single character at least will be deleted)

How to implement AUTO-COMPLETION 

Ctrl+p   to insert the previous matching word

Ctrl+n  to insert the next matching word

Ctrl +x  followed by Ctrl+l to complete a whole line from the buffer

(basically ctrl + x pressing will open a sub-mode from there on we can do a lot of stuff.

for example ctrl + l in submodel gives you to complete the whole line )

More content coming soon ....

UVM Interview Questions - 6

Q36: What is the Difference between UVM_ALL_ON and UVM_DEFAULT?

UVM_ALL_ON and UVM_DEFAULT are identical. As per the UVM reference manual:

UVM_ALL_ON: Set all operations on (default).
UVM_DEFAULT: Use the default flag settings.

It is recommended to use UVM_DEFAULT instead of UVM_ALL_ON even though they both essentially do the same thing today. At some point in time, the class library may add another "bit-flag" which may not necessarily be the DEFAULT.

If you use UVM_ALL_ON, that would imply that whatever flag it is would be "ON".

Q37: What drain time in UVM?

The drain time means the access time that you use before ending the simulation. Suppose if we are done with input traffic to the DUT didn't mean that nothing else would happen from that point as the DUT may have required some additional time to complete any transactions that were still being processed. Setting a drain time adds an extra delay from the time that all objections were dropped to the stop of the simulation, making sure that there were no outstanding transactions inside DUT at that point.

You can set the drain time in the base test at the end_of_elobration phase as shown below:

class test_base extends uvm_test;
  // ...
  
  function void end_of_elaboration_phase(uvm_phase phase);
    uvm_phase main_phase = phase.find_by_name("main", 0);
    main_phase.phase_done.set_drain_time(this, 10);
  endfunction
  
  // ...
endclass

Q38: What is Virtual interface and how Virtual interface is used?

"Virtual interfaces are class data member handles that point to an interface instance. This allows a dynamic class object to communicate with a Design Under Test (DUT) module instance without using hierarchical references to directly access the DUT module ports or internal signals."

Below shown sample code is the easier way to use the virtual interface handles in the UVM environment. 

module top;
  …
  dut_if dif;
  …
  initial begin

    uvm_config_db#(virtual dut_if)::set(null, "*", "vif", dif);

    run_test();

  end
endmodule

class tb_driver extends uvm_driver #(trans1);
  …
  virtual dut_if vif;
  …
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    // Get the virtual interface handle that was stored in the
    // uvm_config_db and assign it to the local vif field.
    if (!uvm_config_db#(virtual dut_if)::get(this, "", "vif", vif))
      `uvm_fatal("NOVIF", {"virtual interface must be set for: ",

     get_full_name(), ".vif"});
   endfunction
  …
endclass 

As shown first the actual interface or physical interface handle, dif, is stored into the uvm_config_db at string location "vif" using the set() command just before the run_test() call in the top level module.

Then it shows the use of the get() function of the uvm_config_db to retrieve the virtual interface handle from the same "vif" location and assign it to the local vif virtual interface handle in the driver class (the same code will be used inside of the monitor class as well).

Q39: How to add a user-defined phase in UVM?

If needed a user can create user-defined phases in the UVM environment. However, this may impact the re-usability of the component. To define a custom phase user need to extend the appropriate base class for phase-type. Following are the available base classes.

    class my_phase extends uvm_task_phase;
    class my_phase extends uvm_topdown_phase;
    class my_phase extends uvm_bottomup_phase;

You can refer to the UVM PHASE IMPLEMENTATION EXAMPLE for complete user-defined phase understanding.

Q40: How interface is passed to components in UVM?

The passing of interface is done using the virtual interface to the component is done using set() and get() methods. consider the below example:

Consider we have defined 2 interfaces as

apb_if intf0(.pclk(clk));

apb_if intf1(.pckl(clk));

Setting the interface:

initial begin

   //put in the database the interface used by APB agent agent0

   uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.env.agent0*", "VIRTUAL_INTERFACE", intf0);

   //put in the database the interface used by APB agent agent1

   uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.env.agent1*", "VIRTUAL_INTERFACE", intf1);

end

Getting the interface:

class cfs_apb_agent extends uvm_component;

   

   //pointer to the interface

   virtual cfs_apb_if vif;

   

   virtual function void build_phase(uvm_phase phase);

      super.build_phase(phase);

     

      if(uvm_config_db::#(virtual apb_if)::get(this, "", "VIRTUAL_INTERFACE", vif) == 0) begin

         `uvm_fatal("ISSUE", "Could not get from the database the virtual interface for the APB agent")

      end

   endfunction

endclass

<< PREVIOUS    NEXT >>

Useful Vim plug-in for efficient coding in Perl

Think of a plug-in with which you can do the following while coding a Perl script:

• Auto addition of file header
• Easy addition of function/frame comment
• Quick inclusion of default code snippet
• Performing syntax check
• Reading documentation about a function
• Converting a full code block to comment, and vice versa
• Help to speed up the code writing with consistency in coding.

One-stop solution for all these things is a perl-support vim plug-in

The Perl-Support Vim Plugin – Perl-IDE offers the easiest way to do all of the above, saving a lot of time and keystrokes.

We have already discussed in an earlier article regarding Use of Scripting languages in VLSI

We will be covering the following in this article

1. How to install perl-support plugin to use it with VIM.

2. Powerful features of the Perl-support plugin.

Steps to install Perl-Support VIM Plug-in

1. Download the plugin from the vim.org website.

Click here to download to go to the download page

Alternatively use below command

cd /usr/src/
wget http://www.vim.org/scripts/download_script.php?src_id=9701

2. Copy the zip archive perl-support.zip to $HOME/.vim and run below command

  unzip perl-support.zip

This command will create following files:

  $HOME/.vim/autoload/mmtemplates/...

  $HOME/.vim/doc/...

  $HOME/.vim/plugin/perl-support.vim

3. Loading of plug-in files must be enabled in $HOME/.vimrc. If not use previously

  filetype plugin on

Create .vimrc if there is none or use the files in $HOME/.vim/perl-support/rc as a starting point.

After done with installation lets get to know about

The Powerful Features of Perl-support

1. Add Automatic Header to *.pl file whenever you create a new file

2. Insert statements

3. Insert frequently used statements

4. Insert special variables

5. insert code snippets and manage templates

6. Run a profiler

7.  Run the script, check the syntax, start the debugger

8. Make integration

Details of all these can be found at 

https://wolfgangmehner.github.io/vim-plugins/perlsupport.html

Use of Scripting languages in VLSI

Very often we come across questions from VLSI engineers that "Which scripting language should a VLSI engineer should learn?".

Well, Shell, Tcl, Perl, and Python are the scripting languages that are commonly used for VLSI front end/back end design automation and related applications. 

TCL: Tcl (pronounced "tickle" or as an initialism) is a high-level, general-purpose, interpreted, dynamic programming language

PERL: Practical Extraction and Reporting Language

PYTHON: Python is a dynamic, object-oriented, high-level programming language that can be used for many kinds of software development/scripting.

Shell Scripting: A shell script is a computer program designed to be run by the Unix/Linux shell which could be one of the following:

The Bourne Shell / The C Shell / The Korn Shell / The GNU Bourne-Again Shell

A shell is a command-line interpreter and typical operations performed by shell scripts include file manipulation, program execution, and printing text.

 

Perl has been in use for several years, but python is increasingly becoming more popular. In the past, we have already shared out views on the advantages of Python. Ref: Advantages of Python over Perl

Tcl is also used mostly for tool interfaces as several EDA tools support that.

If you know any kind of programming, learning a new scripting language will be easy.

Following are some commonly used applications of scripting languages in VLSI:

• Front end RTL/Testbench code compilation and simulation flows
• Automation of running tests in regressions, generating reports, analyzing failures, debug automation
• Connectivity checks, netlist parsing, automatic generation/modification any RTL module/stubs, etc
• Synthesis, P&R tools interfacing, and back end flow.
• Several project management utilities - regression pass rates, trends, bug charts, etc - that helps in tracking projects
• Any other task that is repetitive in workflow and can be automated.

Here is a complete comparison of TCL, PYTHON and PERL.

TCL vs PERL vs PYTHON

UPF - Unified Power Format

This is in continuation of our previous post on Low Power Design Techniques, where we learned about different types of strategies used to reduce the power consumption in integrated circuits. Here we will discuss about UPF (Unified Power Format). We will learn the following related to UPF.

What is UPF?
When does it started?
How to use UPF in design?
Who supports it?

The below flow shows the stages of design flow and where UPF is used.

What is UPF?

The Unified Power Format (UPF). It is intended to ease the job of specifying, simulating, and verifying IC designs that have a number of power states and power islands.

Unified Power Format (UPF) is an industry-wide power format specification to implement low power techniques in a power-aware design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as:

* Which power rails to be routed to individual blocks.

* When blocks are expected to be powered up or shut down. 

* How voltage levels should be shifted between two different power domains. 

* And type of measures taken for memory cells and retention registers contents if the primary power supply to a domain is removed. 

Hence making the design to be more power-efficient. With power becoming an important factor in today's electronic systems, there is a need for a more systematic approach to reduce the power in complex designs; and UPF is developed to address this need.

When does it started?

A Unified Power Format (UPF) technical committee was formed by the Accellera organization, chaired by Stephen Bailey of Mentor Graphics. As a reaction to the Power Forward Initiative, the group was proposed in July 2006 and met on September 13, 2006.[1] It submitted its first draft in January 2007, and a version 1.0 was approved to be published on February 26, 2007. Joe Daniels was a technical editor.

How to use UPF in design?

Tcl, the tool control language is the backbone of UPF, as well as the similar Common Power Format (CPF), Tcl is a scripting language originally created to provide a way to automate the control of design software.

The attraction of Tcl is that command-line commands can be used as statements in a script. Most Tcl implementations are specific to an individual tool. However, the CPF and UPF definitions are unusual in that they are meant to be used with all tools in a power-aware flow – the tools themselves have to determine whether the commands supplied in the Tcl script are relevant to them or not.

The Tcl command “create_power_domain”, for example, is used by UPF-aware tools to define a set of blocks in the design that are treated as one power domain that is supplied differently to other blocks on the same chip. The idea behind this type of command is that power-aware tools read in the description of which blocks in a design can be powered up and down independently. The tools can use that information to determine, for example, how the simulation will behave under different conditions.

For example, a testbench written in SystemVerilog may identify to the simulator that a particular block should be powered down to ensure that other blocks do not access it without checking on power status first.

A transistor-level simulation may use the power definitions to see what happens when supply voltages or substrate bias voltages change. Do all the necessary logic paths meet expected timing when the supply voltage to one block is lowered to save power while others are running at their maximum voltage? Similarly, a static analysis tool may check that the correct level shifters are in place to determine whether blocks in different power domains can communicate.

Who support it?

A number of EDA vendors have chosen to support UPF in their flows, including Mentor Graphics and Synopsys. However, support is not universal. Cadence Design Systems supports the Common Power Format originally developed by the company but which is now administered by the Silicon Integration Initiative but has declared support for the latest version of IEEE 1801, which incorporates a number of features from CPF.

Let us know in the comments if you wish to know about any specific details regarding UPF.

Understanding Logic gates at transistor level : Not Gate

Today we will talk about some basics of digital logic gates. It's about using the transistor for the construction of logic gates. Transistors are used in the construction of logic gates as they act as fast switches. 

When the base-emitter diode is turned on enough to be driven into saturation, the collector voltage with respect to the emitter may be near zero and can be used to construct gates for the TTL logic family. Let's start with simple NOT gate.

1. Not Gate using transistor

NOT gates are single-input devices which have an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”, in other words, it “inverts” (complements) its input signal. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0” giving us the Boolean expression A = Q.

The input of the NOT Gate is connected at the base of the transistor and the output is taken from the collector. The transistor here acts as the switch so when the voltage is applied at the base of the transistor the transistor starts conducting and shorts the output to the ground similarly when no voltage is applied at the input the output is connected to the Vcc as shown thus in this way the circuit implements the NOT function.

Low Power Design Techniques

In today's IOT (Internet Of Things) world there are various wearable/Portable smart devices coming up in the market which are battery operated. These devices also need to be Power efficient such that it can run on battery for a long time. And here the concept of Low Power Design comes into existence.

Different types of strategies used to reduce power consumption. Some of them are listed below.

1. Clock Gating
Clock being the highest frequency toggling signal contributes maximum towards the dynamic power consumption in the SoC even when the flops that are being fed by the clock are not changing their state. So, it is practical to gate the clock from reaching the set of registers or maybe some block in the design. This will ensure that there is no switching activity due to change in the clock and hence reduction in dynamic power consumption.

2. Power gating
Power gating is a technique to shut down the power of a block when it is not required to be On. i.e In Mobile voice processing block can be shut down when the user is not having an incoming or outgoing call. This is the best method of reducing power consumption.

3. Multiple Vt Library cells
Nowadays the user provides the same cells with two different threshold voltage in the library. So that synthesis tools can choose cells depending on the requirement. With low Vt, sub-threshold leakage will increase but speed will also be higher. So for timing critical path synthesis tool will insert low Vt cells and at another path high Vt cell.

4. Dynamic voltage and frequency scaling
Dynamic Voltage and Frequency Scaling (DVFS) describes the use of two power saving techniques (dynamic frequency scaling and dynamic voltage scaling). In this technique same block can be working at the different voltage at the different time .i.e some time it is required to do high computation (complex equation solver) task then it needs more speed so it can operate at high voltage. While some time low computation is required so it can operate at a lower voltage.

5. Supply voltage reduction
As power is directly proportional to voltage (p =iv), with a reduction in voltage, power consumption will reduce. But again with a reduction in voltage will reduce switching speed as well.

6. Multi-voltage design
In SOC some block ( RAM) are such which require higher speed, so that block can be powered with higher voltage. While some block (Peripheral device) which does not needs high speed so that block can be powered with lower voltage, which in turn can reduce leakage power. In earlier days people used to have the same voltage for the whole design which makes it necessary to operate at high voltage. While this new technique, we can achieve leakage reduction.

In upcoming posts, we will discuss more on UPF(Unified Power Format) and low power verification.

Understanding real, realtime and shortreal variables of SystemVerilog

This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage.

We faced some issue with real and realtime variable while writing a timing check.

Below is a simplified example of that check. 

`timescale 1ns/1fs;
module test; 
  real a,b;  
  realtime t1, t2;

initial 
begin 
  #1ns;
  t1 = $realtime;
  #1.8ns;
  t2 = $realtime;
  b = 1.8;
  a = t2 - t1; 

  if(a == b)
    $display("PASS a = %f b = %f", a,b);
  else
    $display("FAIL a = %f b = %f", a,b);

end 
endmodule 

and here is what we got the display

FAIL a = 1.800000 b = 1.800000  

How that happened !!! is really 1.800000 != 1.800000  !!!!

Now let's try something else, instead of using real we use shortreal

`timescale 1ns/1fs;
module test; 
  shortreal a,b;  
  realtime t1, t2;

initial 
begin 
  #1ns;
  t1 = $realtime;
  #1.8ns;
  t2 = $realtime;
  b = 1.8;
  a = t2 - t1; 

  if(a == b)
    $display("PASS a = %f b = %f", a,b);
  else
    $display("FAIL a = %f b = %f", a,b);

end 
endmodule 

Now the result was as expected !!

PASS a = 1.800000 b = 1.800000

To understand this lets go to SystemVerilog LRM. As per LRM 

The real data type is from Verilog-2001, and is the same as a C double. 

The shortreal data type is a SystemVerilog data type, and is the same as a C float.

So float is 32 bit data type and double is 64 bit data type. This sounds cool but still how 1.800000 != 1.800000

No ! it's not only about being 32 or 64 bit data type its more about precision."Precision is the main difference where float is a single precision (32 bit) floating point data type, double is a double precision (64 bit) floating point data type ".

To understand this difference let's go beyond and print the values with more number of digits after decimal point.

In below example we have used both real and shortreal to see the difference.

`timescale 1ns/1fs;
module test; 
  real a,b;
  shortreal c,d;
  realtime t1, t2, t3, t4;

initial 
  begin 
    #1ns;
    t1 = $realtime;
    #1.8ns;
    t2 = $realtime;
    b = 1.8;
    a = t2-t1;

    if(a == b)
      $display("Case1: PASS \na = %1.100f \nb = %1.100f", a,b);
    else
      $display("Case1: FAIL \na = %1.100f \nb = %1.100f", a,b);
  end 


initial 
  begin 
    #1ns;
    t3 = $realtime;
    #1.8ns;
    t4 = $realtime;
    d = 1.8;

    c = t2-t1;

    if(c == d)
      $display("Case2: PASS \nc = %1.100f \nd = %1.100f", c,d);
    else
      $display("Case2: FAIL \nc = %1.100f \nd = %1.100f", c,d);
  end 

endmodule

Here is what the display is

Case1: FAIL 
a = 1.7999999999999998223643160599749535322189331054687500000000000000000000000000000000000000000000000000 
b = 1.8000000000000000444089209850062616169452667236328125000000000000000000000000000000000000000000000000

Case2: PASS 
c = 1.7999999523162841796875000000000000000000000000000000000000000000000000000000000000000000000000000000 
d = 1.7999999523162841796875000000000000000000000000000000000000000000000000000000000000000000000000000000

It's clearly seen that the 64 bit real variable has more precision that that or 32 bit shortreal variable.  

Here one more thing to consider is that we are taking difference of time. Floating point math is not exact. Simple values like 0.1 cannot be precisely represented using binary floating point numbers, and the limited precision of floating point numbers means that slight changes in the order of operations or the precision of intermediates can change the result. That means that comparing two floats to see if they are equal is usually not what you want.

The things will not matter much if you are doing calculations in nanoseconds so we suggest to use shortreal instead of real.

  

2017 VLSI Symposia on VLSI Techology and Circuits

For the past 30 years, the combined annual Symposia on VLSI Technology and Circuits have provided an opportunity for the world’s top device technologists, circuit and system designers to engage in an open exchange of leading edge ideas at the world’s premier mid-year conference for microelectronics technology. Held together since 1987, the Symposia on VLSI Technology and Circuits have alternated each year between sites in the US and Japan, enabling attendees to learn about new directions in the development of VLSI technology & circuit design through the industry’s leading research and development presentations.

The comprehensive technical programs at the two Symposia are augmented with short courses, invited speakers and several evening panel sessions. Since 2012, the Symposia have presented joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees. A single registration enables participants to attend both Symposia.

Online paper submission:

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits, to be held at the Rihga Royal Hotel in Kyoto, Japan from June 5 – 8, 2017. In a departure from previous years, both Symposia (VLSI Technology and VLSI Circuits) will be held on a fully overlapping schedule from June 6 – 8, preceded by Short Courses on June 5.

The deadline for paper submissions to both Symposia is January 23, 2017. Complete details for paper submission can be found online at: http://vlsisymposium.org/authors.html

This year’s Symposia theme is “Harmonious Integration Toward Next Dimensions.” Authors are encouraged to submit papers that showcase innovations that extend beyond single ICs and into the module level, with co-optimization of device technology and circuit/system design, including focus areas in the Internet of Things (IoT), industrial electronics, ‘big data’ management, artificial intelligence (AI), biomedical applications, virtual reality (VR) / augmented reality (AR), robotics and smart cars. These topics will be featured in focus sessions as part of the program.

The Symposium on VLSI Technology seeks technical innovation and advances in all aspects of IC technology, as well as the emerging IoT (Internet of Things) field, including:

• IoT systems & technologies, including ultra-low power, heterogeneous integration, wearable devices, sensors, connectivity, power management, digital/analog, microcontrollers and application processors
• Stand-alone & embedded memories, including technology & reliability for DRAM, SRAM, (3D-)NAND, MRAM, PCRAM, ReRAM and emerging memory technologies
• CMOS Technology, microprocessors & SoCs, including scaling, VLSI manufacturing concepts and yield optimization
• RF / analog / digital technologies for mixed-signal SoC, RF front end; analog, mixed-signal I/O, high voltage, imaging, MEMS, integrated sensors
• Process & material technologies, including advanced transistor process and architecture, modeling and reliability; alternate channel; advanced lithography, high-density patterning; SOI and III-V technologies, photonics, local interconnects and Cu/optical interconnect scaling
• Packaging technologies & System-in-Package (SiP), including through-silicon vias (TSVs), power & thermal management, inter-chip communication, 3D-system integration, as well as yield & test issues
• Photonics Technology & ‘Beyond CMOS’ devices

The Symposium on VLSI Circuits seeks original papers showcasing technical innovations and advances in the following areas:

• Digital circuits, processors and architectures, including circuits and techniques for standalone and embedded processors
• Memory circuits, architectures & interfaces for volatile and non-volatile memories, including emerging memory technologies
• Frequency generation and clock circuits for high-speed digital and mixed-signal applications
• Analog and mixed-signal circuits, including amplifiers, filters and data converters
• Wireline receivers & transmitters, including circuits for inter-chip and long-reach applications
• Wireless receivers & transmitters, including circuits for WAN, LAN, PAN, BAN, inter-chip and mm-wave applications
• Power conversion circuits, including battery management, voltage regulation, and energy harvesting
• Imagers, displays, sensors, VLSI circuits & systems for biomedical, healthcare and wearable applications

Joint Technology & Circuits focus sessions feature invited and contributed papers highlighting innovations and advances in the following areas of joint interest:

• IoT /ULP (Internet of Things / Ultra Low Power) devices: Advanced CMOS processes for ULP, design enablement, design for manufacturing, process/design co-optimization, on-die monitoring of variability and reliability
• New Computing: Artificial intelligence, ‘beyond von Neumann’ computing, machine learning, neuromorphic & in-memory / in-sensor computing
• 2D MOSFETs / New concepts for channel & gate materials: Graphene, MoS2, α-Si / poly-Si or flexible organic materials for ‘More than Moore’ devices
• Emerging memory technology & design: SRAM, DRAM, Flash, PCRAM, RRAM, and MRAM, Memristor, 3D Xpoint memory technologies
• Design in scaled technologies: scaling of digital, memory, analog and mixed-signal circuits in advanced CMOS processes
• 3D & heterogeneous integration: power and thermal management; inter-chip communications, SIP architectures and applications

Best Student Paper Award

Awards for best student paper at each Symposia are chosen based on the quality of the papers and presentations. The recipients will receive a monetary award, travel cost support and a certificate at the opening session of the 2018 Symposium. For a paper to be reviewed for this award, the author must be enrolled as a full-time student at the time of submission, must be the lead author and presenter of the paper, and must indicate on the web submission form that the paper is a student paper.

Sponsoring Organizations

The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers and the IEEE Electron Devices Society.

Further Information, Registration and Official Call for Papers

Visit: http://www.vlsisymposium.org.

Advantages of Python over Perl

In the new competitive generation of chip designing where Time-to-Market is so critical and also the complexity of designs is increasing exponentially.  Adding to that it is also observed that the Verification is always considered the longest pole and takes nearly 70% of the chip design life cycle. Hence any opportunity to automate a  task that is repeatable more than once is considered of most importance to improve the verification productivity. This is where  “scripting” skills are highly valuable for any  Verification engineer.

After many years of writing design and verification automation scripts in Perl and Python, we would like to throw some light on the advantages of using Python.

Maintainability

As we all know, Perl is easy to write but hard to read, especially when someone else has written it. There are multiple ways of writing the same code. Add to this fact that many engineers take pride in writing highly obfuscated Perl that is a pain for others to read.

Maintainability is a critical aspect of any engineering project. Throwing away code and rewriting it is a productivity loss. Unfortunately, this happens a lot with Perl.

Python, on the other hand, has a clean syntax and typically there is only one way of doing what you want. Python code is hence much more readable. Even people who have never written Python code ever can understand it, as the syntax is very “pseudo-code” like. It is also easier to functionalize and modularize code in Python as the language naturally encourages this.

Re-usability

Perl is designed for use and throw. You write something in Perl, run it and then forget about it. It is very difficult to extend the functionality of a Perl script. Typically you would not have organized your code into functions, as Perl syntax does not encourage that. When you try adding some functionality to your Perl script you realize that re-writing it completely is better than re-using the earlier script and extending it.

Python syntax encourages re-usability. The mindset is different. When you write code in Python, you write with future re-usability in mind. This is really tough to do in Perl. Perl encourages shortcuts.

Scale

Writing large pieces of code (more than 50k lines) in Perl exposes the weaknesses in the language. Maintainability, performance, and packaging are big issues. Can I package my application in a way that doesn’t require users to download and install modules used by the application?

Perl encourages users to download and install modules as needed. IT departments are not comfortable with upgrading Perl installations on thousands of server farm nodes. It would be an IT nightmare.

Python distributions, on the other hand, come with a majority of the module libraries included. Also, Python allows the packaging of applications so users do not have to manually download and install all module and library dependencies needed to run an application.

Final words

Perl is great at some things. For example, it has fantastic regular expression capabilities (it can even combine multiple regexp’s and match all of them together!). Perl is a worthy successor to awk.

Bottom line:  For use and throw scripts, Perl is great. But, if your code needs to be checked into a version control system and will potentially be modified by other people, I would prefer Python over Perl.

Transaction Recording In Verilog Or System Verilog

As there is not yet a standard for transaction recording in Verilog or VHDL, ModelSim includes a set of system tasks to perform transaction recording into a WLF file. Transaction modeling allows users to raise the level of description, analysis and debugging of their designs to the transaction level. A transaction represents a transfer of high-level data or control information between the test bench and the design under test (DUT) over an interface or any sequence of signal transitions recorded in the simulation database as a transaction.

The API is the same for Verilog and SystemVerilog. As stated previously, the name "Verilog" refers both to Verilog and SystemVerilog unless otherwise noted.

The recording APIs for Verilog and VHDL are a bit simpler than the SCV API. Specifically, in Verilog and VHDL:

• There is no database object as there is in SCV; the database is always WLF format (a .wlf file).

• There is no concept of begin and end attributes All attributes are recorded with the system task $add_attribute() or add_attribute.

• Your design code must free the transaction handle once the transaction is complete and all use of the handle for relations or attribute recording is complete. (In most cases, SystemC designs ignore this step since SCV frees the handle automatically.)

A transaction has a begin time, an end time, and attributes. Examples of transactions include read operations, write operations, and packet transmissions. The transaction level is the level at which many users think about the design, so it is the level at which you can verify the design most effectively.

Transactions are recorded on a stream. A stream is a collection of transactions, recorded over time. A stream has a name, and usually exists somewhere within the test bench hierarchy – for example a driver might have a stream which represents all the transactions that have occurred on that driver. Each driver defines a collection of attributes ( transaction items ) which are defined by users, and which are meaningful to the transaction. The values of attributes are set for each transaction. Finally, transactions can be linked to each other. A link has a direction and a user-defined name, and specifies a relation between the two transactions.

module top;

    integer stream, tr;

    initial begin

        stream = $create_transaction_stream("Stream");

        #10;

        tr = $begin_transaction(stream, "Tran1");

        $add_attribute(tr, 10, "beg");

        $add_attribute(tr, 12, "special");

        $add_attribute(tr, 14, "end");

        #4;

        $end_transaction(tr);

        $free_transaction(tr);

    end

endmodule

Here,

1. $create_transaction_stream() is used to define a transaction stream. You can use this system task to create one or more stream objects.

 module top;
        integer hStream

        initial begin
            hStream = $create_transaction_stream("stream", "transaction");
            .
            .
        end
        .
        .
    endmodule

2. $begin_transaction is used to start a transaction by providing a valid handle of the transaction as shown below.

integer hTrans;
.
.
 hTrans = $begin_transaction(hstream, "READ");

In this example, we begin a transaction named "READ" on the stream already created. The $begin_transaction system function accepts other parameters to specify: the start time for the transaction, and any relationship information, including its designation as a phase transaction.

The return value is the handle for the transaction. It is needed to end the transaction or record attribute.

3. $end_transaction has a single required argument – the handle of the transaction that is to be ended. It also has a single optional argument, the time in the past that this transaction ended. After a transaction has been ended, the transaction handle can still be used to add attributes and create relations.

$end_transaction( handle transaction [, time endTime])

4. $free_transaction has a single argument – the handle of the transaction to be deleted. Once a transaction is deleted the handle becomes invalid. It cannot be used in any other recording interfaces.

$free_transaction (handle transaction)

5. $add_attribute has two required arguments – a transaction handle on which the attribute is to be created and the attribute that is to be recorded. There is one optional argument of type string named attributeName. This attributeName specifies an alias name for the attribute. If not specified, the name used for the attribute is the actual name of the SystemVerilog object.

$add_attribute( handle transaction,  object attributeValue  [, string attributeName])

6. $add_relation has three arguments – the first two are the two transaction handles which are related. The third argument is the string name of the relation.

$add_relation( handle sourceTransaction,  handle targetTransaction,  string relationshipName)

Build smart tests using uvm_report_catcher

Today we will look into a very useful concept of UVM specially when we are doing any erroneous testing. Its all about modifying the severity, id, action, verbosity or the report string itself before the report is finally issued by the report server. 

Normally in our test environment shout for error when any erroneous scenario like CRC error condition or generation of any error interrupt occurs. And we also write erroneous tests to test these scenarios where we end-up with error messages and tests fails. 

The uvm_report_catcher is used to catch messages issued by the uvm report server. Upon catching a report, the catch method can modify the severity, id, action, verbosity or the report string itself before the report is finally issued by the report server.  The report can be immediately issued from within the catcher class by calling the issue method.

The catcher maintains a count of all reports with FATAL, ERROR or WARNING severity and a count of all reports with FATAL, ERROR or WARNING severity whose severity was lowered.  These statistics are reported in the summary of the uvm_report_server.

Example: 

Report catcher class:

class error_report_catcher extends uvm_report_catcher;

  //new constructor

  virtual function action_e catch();

    if(get_severity() == UVM_ERROR && get_id() == "MON_CHK_NOT_VALID") begin

      set_severity(UVM_INFO);

      return CAUGHT;

    end

    else begin

      return THROW;

    end

  endfunction

endclass : error_report_catcher_c

Use of error catcher in testcase: 

class erroneous_test extends base_test_class;

  // report catcher to suppress errors

  error_report_catcher error_catcher ;

  /// \fn new_constructor

   

  /// \fn build_phase

virtual function void build_phase(uvm_phase phase);

    super.build_phase(phase);

      error_catcher = new();

      uvm_report_cb::add(null,error_catcher) ;

      uvm_config_db#(int)::set(this,“uvc.tx_agent","is_active",UVM_ACTIVE);

         

      // User configurations

      env_cfg.print();

      uvm_config_db#(env_config_c)::set(this, "*" , “env_cfg", env_cfg);

      // Calling the error sequence

      uvm_config_db#(uvm_object_wrapper)::set(this, “uvc.tx_agent.tx_sequencer.main_phase","default_sequence",valid_invalid_seq_c::type_id::get());

  endfunction : build_phase

endclass : erroneous_test