Xilinx Shatters Record with World's Highest Capacity FPGA: Virtex-7 2000T

The Virtex®-7 2000T FPGA is the first device to use 2.5-D IC stacked silicon interconnect technology to deliver "More than Moore" capacity: 2 million logic cells, 6.8 billion transistors - 2x the capacity of the largest competing device.

World’s Highest Capacity FPGA - Now Shipping

The Virtex®-7 2000T FPGA delivers greater than 2X the capacity and bandwidth offered by the largest monolithic devices while delivering the time-to-volume advantages of smaller die. Utilizing innovative 2.5D Stacked Silicon Interconnect (SSI) technology, the Virtex-7 2000T FPGA integrates 2 million logic cells, 6.8 billion transistors and 12.5Gb/s serial transceivers on a single device making it the world’s highest capacity FPGA offering unprecedented system integration in addition to ASIC prototyping and ASIC replacement capabilities.

Industry's Highest System Performance

Virtex-7 FPGAs are optimized for advanced systems requiring the highest performance and highest bandwidth connectivity. The Virtex-7 family is one of three product families built on a common 28nm architecture designed for maximum power efficiency and delivers 2X higher system performance at 50% lower power than previous generation FPGAs.

The Virtex-7 family consists of T, XT and HT devices to meet a wide array of market requirements:

Virtex-7 T devices deliver unprecedented levels of capacity and performance enabling ASIC prototyping, emulation and replacement

• Up to 2M logic cells, 6.8 billion transistors and 12.5Gb/s serial transceivers on a single device
• Enables non-linear integration to reduce board space, lower power and increase system performance
• Delivers highest bandwidth, lowest latency by eliminating multiple chip bottlenecks
• Enables rapid development and emulation of advance node ASICs

Virtex-7 XT devices offer the highest processing bandwidth with high performance transceivers, DSP and BRAM

• Integrates up to 96 10G Base KR  backplane capable  serial transceivers
• 5.3 TMACs of DSP 
• 67 Mbits of internal memory
• >1M logic cells

Virtex-7 HT devices with integrated 28Gbps serial transceivers offer an unprecedented 2.8Tb/s of serial bandwidth

• Up to 16 x 28 Gb/s serial transceivers for ultra-high bandwidth applications
• Optimized for next-generation 100G, nx100G and 400G line cards with CFP2 optical interfaces
• Superior jitter performance to exceed CEI 28G specifications

EasyPath™-7 devices offer a conversion-free path to volume production.

Unified Architecture Enables Scalability and Increases Productivity

Fabricated on a high-performance, low-power (HPL) 28nm process, all 7 series FPGAs share a unified architecture. This innovation enables design migration across the Artix™-7, Kintex™-7, and Virtex-7 families. System manufacturers can easily scale successful designs to address adjacent markets requiring reduced cost and power or increased performance and capability. The adoption of AMBA 4, AXI4 specification as part of the interconnect strategy supporting Plug-and-Play FPGA design further improves productivity with IP reuse, portability, and predictability.

Virtex-7 FPGA Key Capabilities

Maximum Capability	Virtex-7 T Devices	Virtex-7 XT Devices	Virtex-7 HT Devices
Logic density (Logic Cells)	1,955K	1,139K	864K
Peak transceiver speed	12.5Gb/s (GTX)	13.1Gb/s (GTH)	28.05Gb/s (GTZ)
Transceivers	36	96	88
Peak bi-directional serial bandwidth	0.900 Tb/s	2.515Tb/s	2.784Tb/s
DSP throughput (symmetric filter)	2,756 GMACS	5,314 GMACS	5,053 GMACS
Block RAM	46.5Mb	85.0Mb	64.4Mb
PCI Express® interface	Gen2x8	Gen3x8	Gen3x8
I/O pins	1,200	1,100	700

System Solutions Enabled by Virtex-7 FPGAs

Delivering the highest bandwidth with the lowest power, Virtex-7 FPGAs address the insatiable demand for networking infrastructure bandwidth. Delivering up to 2.8Tb/s serial bandwidth, these devices enable communications equipment manufacturers to increase network capacity with next-generation hardware that operates within existing power and cooling footprints.

See How Virtex-7 FPGAs Will Benefit Your Next Design

Application	Description
ASIC Prototyping	Build a highly integrated ASIC prototyping solution with the Virtex-7 2000T. With its high logic and processing capacity, mitigate development risks for large ASIC and ASSP designs.
2x100G OTU4 Transponder/Line Card	Build a 2x100G OTU4 Transponder/Line Card using the only 28nm FPGAs that enable designers to integrate two 100G interfaces into a single FPGA for reduced board space, power, and cost.
10GPON/10GEPON OLT Line Card	Meet aggressive 10G port count integration and cost targets for Passive Optical Network (PON) Optical Line Terminal (OLT) Line Cards that bring high-speed networking to the neighborhood/home.
100GE Line Card	Virtex-7 FPGAs offer the right mix of I/O, memory and logic to enable a single-FPGA implementation of new line cards that deliver increased bandwidth.
100G OTN Muxponder	Virtex-7 FPGA XT devices enable a flexible, single-FPGA, 100G OTN Multiplexing Transponder implementation.
300G Interlaken Bridge	Create a 300G Interlaken Bridge that enables infrastructure scaling with devices that deliver up to 1.9Tbps bandwidth for bridging between MAC-NPU, NPU-Switch, NPU-TCAM using the Interlaken industry standard.
400G Line Card	Be first to market with 400GE Line Cards by designing with the only FPGAs to support 400G serial interfaces with next-generation optics.
Portable RADAR Systems	Enable high performance RADAR systems through low power, multi-channel signal recovery and processing.
Terabit Switch Fabric	Virtex-7 FPGA XT device capabilities enable Terabit Switch Fabric to support proliferating 40G/100G ports in networking infrastructure.

Key Documents

Name	Modified	Size
7 Series FPGAs Overview	09/13/2011	563 KB
7 Series Product Brief
WP385 - Industry’s Highest Bandwidth FPGA Enables World’s First Single-FPGA Solution for 400G Communications Line Cards	11/22/2010	623 KB
WP312 - Xilinx Next Generation 28 nm FPGA Technology Overview	03/26/2011	614 KB
WP389 - Lowering Power at 28 nm with Xilinx 7 Series FPGAs	06/13/2011	1.13 MB
WP380 - Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency	10/21/2011	2.31 MB
WP373 - Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices	10/11/2011	301 KB

Source : http://www.xilinx.com/

Intel to Sell Ivy Bridge Late in Q4 2011

CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.

Intel also stated that Ivy bridge is on target for a late Q4 "qualification for sale", which means that Intel will be begin shipping final products to its customers in the second half of the quarter. This will allow Intel to maintain its tick-tock cadence and keep the claim that a production shrink has been introduced in yet another uneven year (and so that it can state that its 22 nm chips were released in 2011). Of course, that does not mean that you will be able to buy those chips in 2011. According to Otellini, first Ivy Bridge systems should become available in Spring 2012. As Ivy Bridge is introduced and ramping up, Intel expects that its profit margins will improve as well.

Sandy Bridge has, despite an initial hiccup, worked out well for Intel. The company is on track to report $55 billion of revenue for 2011, up more than $11 billion over 2010.

Intel's Ivy Bridge Platform Enters Volume Manufacturing Ahead of Spring 2012 Product Launches

As noted by Tom's Hardware, Intel announced during its earnings conference call this week that its Ivy Bridge platform has entered volume production, with the company expecting to begin deliveries to computer manufacturers by the second half of this quarter. It will, however, take some time for Ivy Bridge to make its way into shipping products, with Intel's partners shooting for a Spring 2012 debut.

“CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun, which is a rather significant achievement as there have been apparently no major hiccups in the implementation of its 3D transistor technology. There has always been the question how Intel defines "volume", but vice president Mooly Eden told me years ago that Intel would only consider a production process volume production if it affects "millions" of processors.”

Intel had previously outlined its Ivy Bridge roadmap as targeting a launch for the first half of 2012, and so the latest news confirming that the company is on track with its new 3-D transistor technology bodes well for an on-time launch.
Ivy Bridge will offer a number of benefits for Apple's notebook lines, opening up the door to quad-core processors in the 13-inch MacBook Pro and bringing significantly faster graphicsand new OpenCL capabilities to the MacBook Air. Ivy Bridge will also support ultra high resolution displays and Intel has committed to Thunderbolt support alongside USB 3.0 in the platform.
A minor refresh to Apple's MacBook Pro line is expected any time now, with the update set to carry the line through until Ivy Bridge is ready.

Switch Level design of 2x1 Multiplexer in Verilog

Below written is a switch level coding example in verilog. Its a code for 2x1 multiplexer.

module mux2_1(q,d,select); //Declared parameter list
output q; //Outputs are declared
input[1:0]d; //Inputs are declared
input select;
wire w; //Internal nets
not(w,select); //Pre-defined gates are used
cmos c1(q,d[0],w,select);
cmos c2(q,d[1],select,w);
endmodule//End Module

enjoy coding…. !!!!

Verilog Module structure

Below code gives basic structure of a verilog module

module M (P1, P2, P3, P4);

input P1, P2;
output [7:0] P3;
inout P4;
reg [7:0] R1, M1[1:1024];
wire W1, W2, W3, W4;
parameter C1 = "This is a string";

initial
begin : BlockName
// Statements
end

always
begin
// Statements
end

// Continuous assignments...
assign W1 = Expression;
wire (Strong1, Weak0) [3:0] #(2,3) W2 = Expression;

// Module instances...
COMP U1 (W3, W4);
COMP U2 (.P1(W3), .P2(W4));

task T1;
input A1;
inout A2;
output A3;
begin
// Statements
end
endtask

function [7:0] F1;
input A1;
begin
// Statements
F1 = Expression;
end
endfunction

endmodule

Johnson Counter

The Johnson counter, also called the twisted ring counter, is a variation of the ring counter, with the inverse output of the most significant flip-flop passed to the input of the least significant flip-flop. The sequence followed begins with all 0's in the register. The final 0 will cause 1's to be shifted into the register from the left-hand side when clock pulses are applied. When the first 1 reaches the most significant flip-flop, 0's will be inserted into the first flip-flop because of the cross-coupling between the output and the input of the counter.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Ring counters

Ring counter

A ring counter is a circular shift register with only one flip-flop being set at any particular time; all others are cleared. The single bit is shifted from one flip-flop to the other to produce the sequence of timing signals.

Links:

• Different type of counters
• Binary counters
• Up/down counters
• Loadable counters
• BCD Counter
• Johnson counters