UVM Tutorial - The DUT

This training guide will focus on showing how we can build a basic UVM environment, so the device under test was kept very simple in order to emphasize the explanation of UVM itself.

The DUT used is a simple ALU, limited to a single operation: the add operation. The inputs and outputs are represented in Figure 1.1.

Figure 1.1: Representation of the DUT’s inputs/outputs

This DUT takes two values of 2 bits each, ina and inb, sums them and sends the result to the output out. The inputs are sampled to the signal of en_i and the output is sent at the same time en_o is signalled.

The operation of the DUT is represented as a timing diagram and as a state machine in Figure 1.2.

Figure 1.2: Operation of the DUT

Below is the code for sample DUT

UVM Introduction

As digital systems grow in complexity, verification methodologies get progressively more essential. While in the early beginnings, digital designs were verified by looking at waveforms and performing manual checks, the complexity we have today don’t allow for that kind of verification anymore and, as a result, designers have been trying to find the best way to automate this process.

The SystemVerilog language came to aid many verification engineers. The language featured some mechanisms, like classes, covergroups and constraints, that eased some aspects of verifying a digital design and then, verification methodologies started to appear.

UVM is one of the methodologies that were created from the need to automate verification. The Universal Verification Methodology is a collection of API and proven verification guidelines written for SystemVerilog that help an engineer to create an efficient verification environment. It’s an open-source standard maintained by Accellera and can be freely acquired in their website.

By mandating a universal convention in verification techniques, engineers started to develop generic verification components that were portable from one project to another, this promoted the cooperation and the sharing of techniques among the user base. It also encouraged the development of verification components generic enough to be easily extended and improved without modifying the original code.

All these aspects contributed for a reduced effort in developing new verification environments, as designers can just reuse testbenches from previous projects and easily modify the components to their needs.

These series of webpages will provide a training guide for verifying a basic adder block using UVM. The guide will assume that you have some basic knowledge of SystemVerilog and will require accompaniment of the following resources:

• Accellera’s UVM User’s Guide 1.1

• Accellera’s UVM 1.1 Class Reference

• Verification Academy’s UVM Cookbook

This guide will be divided in 3 different parts:

• The first part, starting on chapter 1, will explain the operation of the device under test (DUT): the inputs, the outputs and the communication bus

• The second part, starting on chapter 2, will give a brief overview of a generic verification environment and the approach into verifying the DUT

• The third part, starting on chapter 3, will start to describe a possible UVM testbench to be used with our DUT with code examples. It’s important to consult to the external material in order to better understand the mechanism behind the testbench.

Transient Materials - Electronics that melt away

Imagine tossing your old phone in the toilet, watching it dissolve and then flushing it down, instead of having it wind up in a landfill. Scientists are working on electronic devices that can be triggered to disappear when they are no longer needed.

The technology is years away, but Assistant Professor Reza Montazami and his research team in the mechanical engineering labs at Iowa State University have published a report that shows progress is being made. In the two years they've been working on the project, they have created a fully dissolvable and working antenna.

"You can actually send a signal to your passport via satellite that causes the passport to physically degrade, so no one can use it," Montazami said.

The electronics, made with special "transient materials," could have far-ranging possibilities. Dissolvable electronics could be used in medicine for localizing treatment and delivering vaccines inside the body. They also could eliminate extra surgeries to remove temporarily implanted devices.The military could design information-gathering gadgets that could complete their mission and dissolve without leaving a trace.

The researchers have developed and tested transient resistors and capacitors. They’re working on transient LED and transistor technology, said Montazami, who started the research as a way to connect his background in solid-state physics and materials science with applied work in mechanical engineering.

As the technology develops, Montazami sees more and more potential for the commercial application of transient materials.

EDA Playground–An Awesome Online Tool

Many times we use the web to find code examples and tutorials. However, often the examples were incomplete. Sometimes they were missing the necessary code to hook the example into a real design. Other times, the code examples had syntax errors.

Sometime we are presented with a working design, with lines stripped out, but with undefined variables and dangling commas left in. Other times the code examples simply did not work on my simulator. All this resulted in endless frustration to us. I knew there had to be a better way, EDA Playground is one.

EDA Playground is a free web application that allows users to edit, simulate (and view waveforms), synthesize, and share their HDL code. Its goal is to accelerate the learning of design and testbench development with easier code sharing and with simpler access to simulators and libraries. EDA Playground is specifically designed for small prototypes and examples (it is not intended to be used for a full-blown FPGA or ASIC design).

EDA Playground gives engineers immediate hands-on exposure to simulating SystemVerilog, Verilog, VHDL, C++/SystemC, and other HDLs. All you need is a web browser. The goal is to accelerate learning of design/testbench development with easier code sharing, and with simpler access to EDA tools and libraries. EDA Playground is specifically designed for small prototypes and examples.

• With a simple click, run your code and see console output in real time. Pick another simulator version and run it again.
• View waves for your simulation using EPWave browser-based wave viewer.
• Save your code snippets. Share your code and simulation results with a web link. Perfect for web forum discussions or emails. Great for asking questions or sharing your knowledge.
• Quickly try something out
  • Try out a SystemVerilog feature before using it on your project.
  • Try out a library that you’re thinking of using.
  • Modify another engineer’s shared code and re-run it.
• Eliminate environment differences. Since the code always executes in the same environment, everyone will see the same result on a subsequent re-run.
• Browse and use a large repository of working code examples and templates.

 

Google To Develop Quantum Processors

Google was one of the early backers of a new approach to quantum computing adopted by a company called D-Wave. The company offers boxes that perform a process called quantum annealing instead of the more typical approach, which involves encoding information in a quantum state of a collection of entangled qubits. Although whatever D-Wave is doing is clearly quantum, it's still not clear that it offers a speedup compared to classical computers.

So rather than keeping all its eggs in D-Wave's basket, Google's "Quantum A.I. Lab" announced that it is starting a collaboration with an academic quantum computing researcher, John Martinis of the University of California-Santa Barbara. Martinis' group focuses on creating fault-tolerant qubits using a solid-state superconducting structure called a Josephson junction. By linking several of these junctions and spreading a single quantum state across them, it's possible to reach fidelities of over 99 percent when it comes to storing the quantum state.

Quantum states tend to be fragile and decay when they interact with their environment, so a lot of labs are working on making qubits that are more robust or have error correcting ability. Josephson junctions are one possible approach to this, but they have the advantage of being on familiar turf for computing companies, since they can be made by standard fabrication techniques (although they still need to be chilled to near absolute zero).

Google made it clear that it's not turning its back on D-Wave; the new work will be done in parallel. As for quantum computing itself, this is interesting news. A quick look at our past coverage makes it clear that there are a number of technologies that appear to be getting close to the point where they could be used to create a multi-qubit machine. Google's decision to push hard on one of these approaches could narrow the field—either by getting Josephson junctions to work or by showing that there are severe limitations to them.

Do You Know Internet Of Things !!!

The Internet of Things (IoT, also Cloud of Things or CoT) refers to the interconnection of uniquely identifiable embedded computing like devices within the existing Internet infrastructure. The Internet of Things is a scenario in which objects, animals or people are provided with unique identifiers and the ability to transfer data over a network without requiring human-to-human or human-to-computer interaction. IoT has evolved from the convergence of wireless technologies, micro-electromechanical systems (MEMS) and the Internet. The creativity of this new era is boundless, with amazing potential to improve our lives.

Here are the six main attributes that make "things" a part of the Internet Of Things, or IoT:

• Sensors: IoT devices and systems include sensors that track and measure activity in the world. One example is Smartthings' open-and-close sensors that detect whether or not a drawer, window, or door in your home is open or closed.
  
• Connectivity: Internet connectivity is either contained in the item itself, or a connected hub, smartphone, or base station. If it's the latter, then the base station will likely be collecting data from an array of sensor-laden objects, and relaying data to the cloud and back.
  
• Processors: Just like any computing device, IoT devices will contain some computing power "under the hood," if only to be able to parse incoming data and transmit it.
  These characteristics all apply to today's smartphones, of course, but many IoT devices will also need to be equipped with several special features to be truly useful. These will differentiate IoT devices, particularly remote ones, from today's smartphones.
  
• Energy-efficiency: Many devices in the IoT may be difficult, costly, or dangerous to access for charging or battery replacement. One may even think of the Mars Curiosity Rover as an example of such a device. Therefore, they may need to be able to operate for a year or more unattended using a conservative amount of energy or be able to wake up only periodically to relay data.
  
• Cost-effectiveness: Objects that contain sensors may need to be distributed broadly to be useful, as in the case of sensors in food products in supermarkets that would indicate if an item has spoiled. These would need to be relatively inexpensive to purchase and deploy.
  
• Quality and reliability: Some IoT devices will need to operate in harsh environments outdoors and for extended periods of time.
  
• Security: IoT devices may need to relay sensitive or regulated information such as health-related data, so data security will be critical.

Internet Of Things explained by Arlen Nipper.
Arlen Nipper has been designing embedded computer hardware and software for 33 years. Arlen graduated from Oklahoma State University and worked in the oil patch for 10 years learning tons of useful stuff about "how things work" in the real world.

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VHDL Coding Tips For Excellent Design

Here are the Ten Commandments of Excellent Design:

1. All state machine outputs shall always be registered
2. Thou shalt use registers, never latches
3. Thy state machine inputs, including resets, shall be synchronous
4. Beware fast paths lest they bite thine ankles
5. Minimize skew of thine clocks
6. Cross clock domains with the greatest of caution. Synchronize thy sig- nals!
7. Have no dead states in thy state machines
8. Have no logic with unbroken asynchronous feedback lest the fleas of myriad Test Engineers infest thee
9. All decode logic must be crafted carefully—eschew asynchronicity
10. Trust not thy simulator—it may beguile thee when thy design is junk

How to Write Ten-Commandment Code

Conforming to the Ten Commandments is not difficult. In this section you’ll see how to write VHDL (your author doesn’t do Verilog, but the translation is easy) that complies with the rules. Robust design and first-silicon success are the goals!

The philosophy behind Ten-Commandment code is that synthesizers are not to be trusted too much. Most of the code you will see is close to the structural level; some more overtly than others. Most of the code is self-explanatory. It is assumed that the reader is familiar with VHDL. Signal names are also obvious to anyone “skilled in the art.”

How to Create a Flip-Flop

One of the basic primitives that we need to create robust synchronous designs is the D-type flip-flop. Look at the code in Code Sample 1: A D-type Flip Flop

-- VHDL Code for a D-Type Flip-Flop with an -- Asynchronous Clear

D_Type_Flip_Flop: process(Reset_n, Clock_In)

  begin

    if (Reset_n = ’0’) then

      Q_Output <= ’0’ after 1 ns;

  elsif (Clock_In’event and Clock_In = ’1’) then

      Q_Output <= D_Input after 1 ns;

  end if;

end process D_Type_Flip_Flop;

This flip-flop has the following properties:

• An asynchronous active-low clear input sets the Q output to zero.
• It is triggered on the rising edge of the clock.

How to Create a Latch

While the Ten Commandments specifically forbid the use of latches, there are still those heretics who will insist on the use of latches. The code to instantiate a transparent latch is shown in Code Sample 2: A Transparent Latch

-- VHDL Code for a Transparent Latch

Latch_Data: process(Latch_Open, D_Input)

  begin

    if (Latch_Open = ’1’) then

      Latched_Data <= D_Input;

    -- If Latch_Open = 0, then Latched_Data keeps its old value, -- i.e. the latch is closed.

    end if;

end process Latch_Data;

This latch has the following properties:

• A latch control that opens the latch when high (the latch is transparent).

How to Create a Metastable- Hardened Flip-Flop

The use of a metastable-hardened flip flop is nothing more than the direct instantiation of a suitable library element in this case, a “dfntns” flip-flop. This is pure structural VHDL. The component declaration is shown in Code Sample 3:  A Metastable-Hardened Flip-Flop, Component Declaration

-- VHDL Code for a Nice Metastable-Hardened Flip-Flop

component dfntns

  Port (

    CP : In std_logic;

    D : In std_logic;

    Q : Out std_logic

  );

end component;

To use the flip-flop in your circuit, instantiate it as shown in Code Sample 4: A Metastable-Hardened Flip-Flop, Instantiation

-- VHDL Code to Instantiate the Metastable-Hardened Flip-Flop

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

  D => D_Input,

  CP => Clock_In,

  Q => Q_Output

  );

This flip-flop has the following properties:

• A maximum clock-to-out time under worst-case setup and hold time violations. This time is available in the library element specifications.

The Care and Feeding of Toggle Signals

Receiving a Toggle Signal

The Ten Commandments paper suggested that a method for exchanging single- point information across clock domains is by the use of toggle signals. Here, it is assumed that the toggle event should generate an active-high pulse to pass to a state machine. Every toggle—rising edge and falling edge—must create the pulse. In addition, the pulse must be synchronized correctly to the receiver’s clock. The code to accomplish this is shown in Code Sample 5: Receiving a Toggle Signal

-- VHDL Code to Create a Pulse from an Asynchronous -- Toggle Signal

-- First, use a metastable-hardened flip-flop to synchronize the -- toggle input

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

  D => Handshake_T,

  CP => Clock_In,

  Q => Sync_Handshake_T

  );

-- Now pass the synchronized toggle through another flip-flop

Toggle_Reg_Proc: process(Clock_In)

  begin

    if (Clock_In'event and Clock_In = ’1’) then

      Reg_Handshake_T <= Sync_Handshake_T after 1 ns;

    end if;

  end process Toggle_Reg_Proc;

-- Finally XOR the two synchronized signals to create a pulse

Toggle_Pulse <= Reg_Handshake_T xor Sync_Handshake_T;

When synthesizing this code, remember to use the “fix hold” option so a fast path doesn't occur between the two flip-flops in this circuit.

Generating a Toggle Signal

Recall that a toggle signal is generated by simply inverting a level to pass the information. The trivial code to do this is shown in Code Sample 6:  Generating a Toggle Signal

The suffix “_T” is used to denote a toggle signal.

-- VHDL Code to Create a Toggle Signal

Handshake_T <= not (Handshake_T) after 1 ns;

Coding State Machines
The creation of state machines is a mixture of art and science. A well-crafted state machine will possess a sense of elegance; it will be appealing, both functionally and visually.
Here, a very simple example is presented as an illustration of state machine design. The state diagram for the Flintstones State Machine is shown in figure below popularly known as The Flintstones State Machine.

The Flintstones State Machine operates as follows:

1. The State Machine has two states, State Bed and State Rock.
2. There is one output, Fred, which takes the value 0 in State Bed and 1 in State Rock.
3. A reset, caused by a low level on Reset_n, puts the State Machine into State Bed.
4. The State Machine waits in State Bed while Barney is low, and enters State Rock when Barney goes high.
5. The State Machine then waits in State Rock while Wilma is low, and returns to State Bed when Wilma goes high.

Implementing the Flintstones State Machine

An example implementation of the Flintstones State Machine is shown in Code Sample 7 below:

-- VHDL Code to Implement the Flintstones State Machine

Flintstones_SM_Proc: process(Sync_Reset_n, Clock_In)

  -- Enumerate state types:

  type Flintstones_Statetype is (

  Bed, Rock

  );

  -- define the state variable:

  variable Flint_State: Flintstones_Statetype;

  -- Here’s the state machine:

  begin

  -- Define the asynchronously set reset states...

    if (Sync_Reset_n = ’0’) then

      Fred <= ’0’ after 1 ns;

      Flint_State := Bed

      -- Default conditions for each output, in this case identical to the -- reset state:

    elsif (Clock_In’event and Clock_In = ’1’) then

      Fred <= ’0’ after 1 ns;

    -- Here are the state transitions:

    case Flint_State is

      when Bed =>

      -- Transition from Bed to Rock:

        if (Barney = ’1’) then

          Fred <= ’1’ after 1 ns;

          Flint_State := Rock;

          -- Holding term in Bed:

        else

          Flint_State := Bed;

        end if;

      when Rock =>

        -- Transition from Rock to Bed:

        if (Wilma = ’1’) then

          Fred <= ’0’ after 1 ns;

          Flint_State := Bed;

        -- Holding term in Rock:

        else

          Fred <= ’1’ after 1 ns;

          Flint_State := Rock;

        end if;

      -- Default term for dead states:

      when others =>

        Flint_State := Bed;

    end case;

  end if;

end process Flintstones_SM_Proc;

Notes on the State machine Implementation

For the most part, the Flintstones State Machine’s operation should be clear. A few points are worth noting, however:

1. The reset signal (Sync_Reset_n) is synchronized with Clock_In before being sent to the State Machine.
2. Barney and Wilma must also be synchronous to Clock_In; at the very least, there must be an assurance that the State Machine’s state and output regis- ter’s setup and hold times are not violated.
3. This design assigns a default value to each output and to the state variable before entering the case statement. This ensures that only those signals that are not taking default (usually inactive) values need be listed in the case statement. This is optional; it is entirely reasonable to list every signal under each transition term, including inactive signals.
4. Note that the output signal Fred comes directly from a D-type flip-flop: it is not a decode of the state variable. This ensures Fred’s cleanliness (so to speak).
5. The “when others” in the case statement handles the possibility that the State Machine might end up in a dead state.

The code examples in this tutorial should be considered as examples only. There are many ways to code excellent VHDL; this code is a place to start. If you have a neat snippet of VHDL to add to the list, then please post your valuable comments below.