Mega Processor to Understand Micro Processor

Have you ever imagine how the work or what's going on inside? Think about a bigger version of a microprocessor where you can walk inside and look how it is working in real.

You may have heard that your smartphone contains more computing power than all the computers used on the Apollo mission combined. But imagine taking the computing power of a Super Nintendo, and packing it into a computer the size of--a living room?

The "mega-processor" is essentially a blown up version of a tiny chip that allows you to see how all the elements of a computer chip join together and how it actually works.

A Cambridge resident has finished building a 10-metre wide and 2-metre high computer in his living room, which he uses to play the video game Tetris.

James Newman took four years and £40,000 to build the processor which works exactly like a small microprocessor chip in a regular desktop computer or laptop that's about the size of a sim card.

This room-sized megaprocessor has 40,000 transistors, 10,000 LED lights, weighs around half a tonne (500kg) and burns 500W of electricity, according to Newman, who explains the entire contraption in a video.

James Newman said his Mega Processor relies almost entirely on the hand-soldered components, and will ultimately demonstrate how data travels through and is processed in a simple CPU core. He's just finished putting together the general purpose registers, and in May completed the arithmetic and logic unit.

Each transistor acts like a digital switch, and can be chained together to form huge decision-making circuits that execute software, instruction by instruction.

Newman, whose background is in software development and FPGA programming, told The Register he has spent about £40k on the project to date. He started planning the processor in 2012, and began building the beast a year later.

The World's First 1,000 Processor Chip ( KiloCore Chip )

A team of scientists from the University of California has created the world's first microchip with 1,000 independent processors. Called 'KiloCore' chip, it is also claimed to be the world's fastest chip ever designed at a university. The chip, which was presented this week at the 2016 Symposium on VLSI Technology and Circuits, is capable of 1.78 trillion instructions per second and contains 621 million transistors. The partially Department of Defense-funded KiloCore chip was ultimately built by IBM using existing 32 nanometer semiconductor fabrication technology.

Unfortunately, a 1,000 core chip isn't something that could just be plugged into the next line of MacBook Pros. It wouldn't even really suffice as a graphics processor, where massively parallel computation is the norm. In fact, many GPUs exceed the 1,000 cores of the UC Davis chip, but with the caveat that the individual cores are directed according to a central controller. The KiloCore, by contrast, is built from completely independent cores capable of running completely independent computer programs.

Here's all you need to know about the chip:

• This microchip has been designed by a team at the University of California, Davis, Department of Electrical and Computer Engineering.
• KiloCore chip executes instructions more than 100 times more efficiently than a modern laptop processor.
• Each processor core can run its own small program independently of the others, which is a fundamentally more flexible approach than the Single-Instruction-Multiple-Data approaches utilized by processors such as graphics processing unit (GPU). Because each processor is independently clocked, it can shut itself down to further save energy when not needed.
• The chip has been fabricated by IBM using its 32nm CMOS technology. KiloCore's each processor core can run its own small program independently of the others.
• Cores operate at an average maximum clock frequency of 1.78 GHz, and they transfer data directly to each other rather than using a pooled memory area that can become a bottleneck for data.

The independence of the cores makes the KiloCore chip a multiple instruction multiple data (MIMD) computer. This is in contrast to the more typical single instruction multiple data (SIMD) variety of parallel computation, as would be expected in a graphics processor. A SIMD machine's version of parallelism is to implement the same single operation across many different cores - that is, do the same thing to many different units of data. This is the norm in image processing, for example, where a lot of different pixels holding different a lot of different values are all updated in the same way. A MIMD machine can be expected to do much more complex calculations.

Together, the 1,000 processors can execute 115 billion instructions per second while dissipating only 0.7 Watts. As noted in a UC Davis press release, this power requirement is low enough that it could be supplied by a single AA battery, achieving an efficiency of around 100 times that of a normal laptop processor.

The energy savings here largely has to do with the abandoning of the traditional system memory architecture, in which data for multiple cores is stored in a central RAM unit. Rather than sharing data in this way, the KiloCore chip uses a built-in networking scheme in which data is transferred directly between the different processors using packet- and circuit-switched networking.

Radix number systems and conversions

We have learned and use the decimal numbering system simply because humans are born with ten fingers! Hence, the numeric system we is the decimal number system, but this system is not convenient for machines since the information is handled codified in the shape of ON or OFF bits.

This means, we have to learn the binary system in addition to the decimal system. We also will discuss the octal and hexadecimal systems because conversion to/from binary is easy and numbers in these systems are easier to read than binary numbers for humans. 

This way of codifying takes us to the necessity of knowing the positional methods of calculation which will allow us to express a number in any base where we need it.

A base of a number system or radix defines the range of values that a digit may have.

Binary Number System

In the binary system or base 2, there can be only two values for each digit of a number, either a "0" or a "1".

Digital and computer technology is based on the binary number system, since the foundation is based on a transistor, which only has two states: on or off.

Each digit of the number is called a bit or which is a short for binary digits.

• An 8-bit group is referred to as a Byte
• An 4-bit group is referred to as a nibble

Each bit is weighted based on its position in the sequence (powers of 2) from the Least

Significant Bit (LSB) to the Most Significant Bit (MSB).

Each bit must be less than 2 which means it has to be either 0 or 1.

For example (1010.11)2 is evaluated as:

(1010.11)2 = 8 + 0 + 2 + 0 + 0.5 + 0.25 = (10.75)10 

Note: The general term for decimal point is radix point

In binary, the count starts at 0 (called 0-referencing), where in decimal, the count typically starts

with 1 (called 1-referencing) 

Octal Number System

In the octal system or base 8, there can be eight choices for each digit of a number:

"0", "1", "2", "3", "4", "5", "6", "7".

Octal number systems are used by humans as a representation of long strings of bits since they are:

• Easier to read and write, for example 347 in octal is easier to read and write than 011100111 in binary.
• Easy to convert (Groups of 3 or 4)
• The most common way is to use Hex to write the binary equivalent; two hexadecimal digits make a Byte (groups of 8-bit), which are basic blocks of data in Computers.

Decimal Number System

In the decimal system or base 10, there are ten different values for each digit of a number:

"0", "1", "2", "3", "4", "5", "6", "7", "8", "9".

Decimal number system is default and easy to use for us. For example when you see a number 56 your assumption is that its base or radix is 10 i.e. “56 base 10”.

• Each digit is weighted based on its position in the sequence (power of 10) from the Least Significant Digit (LSD, power of 0) to the Most Significant Digit (MSD, highest power).  
• Each digit must be less than 10 (0 to 9) 

Hexadecimal Number System

In the hexadecimal system, we allow 16 values for each digit of a number:

"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "A", "B", "C", "D", "E", and "F".

Where “A” stands for 10, “B” for 11 and so on.

Conversion among different radices

1. Convert from Decimal to Any Base

Let’s think about what you do to obtain each digit. As an example, let's start with a decimal number 1234 and convert it to decimal notation. To extract the last digit, you move the decimal point left by one digit, which means that you divide the given number by its base 10.

 1234/10 = 123 + 4/10

The remainder of 4 is the last digit. To extract the next last digit, you again move the decimal point left by one digit and see what drops out.

 123/10 = 12 + 3/10

The remainder of 3 is the next last digit. You repeat this process until there is nothing left. Then you stop. In summary, you do the following: 

Conversion of decimal number to binary

Now, let's try a nontrivial example. Let's express a decimal number 1341 in binary notation. 

Note that the desired base is 2, so we repeatedly divide the given decimal number by 2. 

Conversion of decimal number to octal

Now, let's express the same decimal number 1341 in octal notation. 

Conversion of decimal number to hexadecimal

Let's express the same decimal number 1341 in hexadecimal notation. 

The easiest way to convert fixed point numbers to any base is to convert each part separately. We begin by separating the number into its integer and fractional part. The integer part is converted using the remainder method, by using a successive division of the number by the base until a zero is obtained. At each division, the reminder is kept and then the new number in the base r is obtained by reading the remainder from the lat remainder upwards.

The conversion of the fractional part can be obtained by successively multiplying the fraction with the base. If we iterate this process on the remaining fraction, then we will obtain successive significant digit. This methods form the basis of the multiplication methods of converting fractions between bases.

Example:

Convert the decimal number 3315 to hexadecimal notation. What about the hexadecimal equivalent of the decimal number 3315.3? 

Solution:

Conversion of Any Base to Decimal
Let's try to understand what a decimal number means. For example, 1234 means that there are four boxes (digits); and there are 4 one's in the right-most box (least significant digit), 3 ten's in the next box, 2 hundred's in the next box, and finally 1 thousand's in the left-most box (most significant digit). The total is 1234:

or simply, 1*1000 + 2*100 + 3*10 + 4*1 = 1234

Thus, each digit has a value: 10^0 =1 for the least significant digit, increasing to 10^1 =10, 10^2 =100, 10^3 =1000, and so forth.

Likewise, the least significant digit in a hexadecimal number has a value of

16^0 =1 for the least significant digit, increasing to
16^1 =16 for the next digit,
16^2 =256 for the next,
16^3 =4096 for the next, and so forth.

Thus, 1234 means that there are four boxes (digits); and there are 4 one's in the right-most box (least significant digit), 3 sixteen's in the next box, 2 256's in the next, and 1 4096's in the left-most box (most significant digit). The total is:

1*4096 + 2*256 + 3*16 + 4*1 = 4660

In summary, the conversion from any base to base 10 can be obtained from the formulae

Where b is the base, di the digit at position i, m the number of digit after the decimal point, n the number of digits of the integer part and X10 is the obtained number in decimal. This form the basic of the polynomial method of converting numbers from any base to decimal

Example: Convert 234.14 expressed in an octal notation to decimal.

Example: Convert the hexadecimal number 4B3 to decimal notation. What about the decimal equivalent of the hexadecimal number 4B3.3?

Example:  Convert 234.14 expressed in an octal notation to decimal.

UVM Interview Questions - 5

Q31: What is virtual sequencer and virtual sequence in UVM?

A virtual sequencer is a sequencer that is not connected to a driver itself, but contains handles for sequencers in the testbench hierarchy. It is an optional component for running of virtual sequences - optional because they need no driver hookup, instead calling other sequences which run on real sequencers.

A sequence which controls stimulus generation across more than one sequencer, coordinate the stimulus across different interfaces and the interactions between them. Usually the top level of the sequence hierarchy i.e. 'master sequence' or 'coordinator sequence'. Virtual sequences do not need their own sequencer, as they do not link directly to drivers. When they have one it is called a virtual sequencer.

Here is a good article which explains how to use virtual sequence and virtual sequencer.

http://www.learnuvmverification.com/index.php/2016/02/23/how-virtual-sequence-works-part-1/

Q32: How set_config_* works?

The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances.

Configuration is a mechanism in UVM that higher level components in a hierarchy can configure the lower level components variables. Using set_config_* methods, user can configure integer, string and objects of lower level components. Without this mechanism, user should access the lower level component using hierarchy paths, which restricts re-usability.

This mechanism can be used only with components. Sequences and transactions cannot be configured using this mechanism. When set_config_* method is called, the data is stored w.r.t strings in a table. There is also a global configuration table.

Higher level component can set the configuration data in level component table. It is the responsibility of the lower level component to get the data from the component table and update the appropriate table.

following are the method to configure integer, string and object of uvm_object based class respectively.

function void set_config_int (string inst_name, string field_name, uvm_bitstream_t value)

function void set_config_string (string inst_name, string field_name, string value)

function void set_config_object (string inst_name, string field_name, uvm_object value, bit clone = 1)

Q33: What are the advantages of uvm RAL model ?

• The RAL (register abstraction layer) provides accesses to DUT and also keeps a track of register content of DUT.
• UVM RAL can be used to automate the creation of high level, object oriented abstraction model of registers and memory in DUT.
• Register layer makes the register abstraction and access of its contents independent of the bus protocol which is used to transfer data in and out of registers inside the design.
• Hierarchical model provided by RAL makes the reusability of test bench components very easy.
• The changes in initial configuration of registers or specifications can be easily communicated in the entire environment. RAL layer supports both front door and backdoor access. The backdoor access does not use the bus interface rather it uses the HDL defined paths for direct communication with the device. Thus in zero simulation time the registers of device can be reconfigured using the backdoor access and verification can be started.
• One more advantage of backdoor access is that it can be used for verify if the access through front door are happening correctly. To achieve this the front door, write is verified using backdoor read.

Q34: What are the different override types?

Two type of overriding is supported by UVM

1. Type overriding

Type overriding means that every time a component class type is created in the Testbench hierarchy, a substitute type i.e. derived class of the original component class, is created in its place. It applies to all the instances of that component type.

Syntax:

<original_type>::type_id::set_type_override(<substitute_type>::get_type(), replace);

where “replace” is a bit which is when set equals to 1, enables the overriding of an existing override else existing override is honoured.

2. Instance overriding

In Instance Overriding, as name indicates it substitutes ONLY a particular instance of the component OR a set of instances with the intended component. The instance to be substituted is specified using the UVM component hierarchy.

Syntax:

<original_type>::type_id::set_inst_override(<substitute_type>::get_type(), <path_string>);

Where “path_string” is the hierarchical path of the component instance to be replaced.

Q35: Explain end of simulation in UVM?

Different approaches to finish the UVM Test using the objection mechanism are

1. Raising & dropping objections

raise_objection() and drop_objection() are the methods to be used to do that.

2. phase_ready_to_end

phase_ready_to_end method is executed automatically by UVM once ‘all dropped’ condition is achieved during Run Phase.

3. set_drain_time

Another approach supported by UVM is setting the drain time for the simulation environment. Drain time concept is related to the extra time allocated to the UVM environment to process the left over activities e.g. last packet analysis & comparison etc after all the stimulus is applied & processed.

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IBM steps forward to replace Silicon Transistors with Carbon Nanotubes

Carbon Nanotube

The breakthrough is that - IBM improves carbon nanotube scaling below 10nm. How ever before calling it as breakthrough we should also check out what other giants like Intel, AMD, TSMC or Samsung is working on. This breakthrough has relation with the Moore's Law. Yes you got right..!!It says that the transistor counts double only every 18 month or so. It’s the time that Intel marks 40 years of the 4004 microprocessor and here now lying some fear that progress will soon hit a wall.

You can refer to my post History and Evolution of Integrated Circuits where it shows clear progress of semiconductor industry.

But not to worry, IBM has developed a way that could help the semiconductor industry continue to make ever more dense chips to support Moore's law. These chips will be both faster and more power efficient.

Few glimpse of carbon nanotube transistors

• Carbon nanotube transistors can operate at ten nanometers
• Equivalent to 10,000 times thinner than a strand of human hair
• Less than half the size of today’s leading silicon technology
• Could also mean wearables that attach directly to skin and internal organs

Here I have an animation for Animated Nanofactory in Action.

As a result of this the devices will become smaller, increased contact resistance for carbon nanotubes has hindered performance gains until now.

These results could overcome contact resistance challenges all the way to the 1.8 nanometer node – four technology generations away.

A project at IBM is now aiming to have transistors built using carbon nanotubes ready to take over from silicon transistors soon after 2020. According to the semiconductor industry’s roadmap, transistors at that point must have features as small as five nanometers to keep up with the continuous miniaturization of computer chips.

IBM has previously shown that carbon nanotube transistors can operate as excellent switches at channel dimensions of less than ten nanometers – the equivalent to 10,000 times thinner than a strand of human hair and less than half the size of today’s leading silicon technology.

IBM's new contact approach overcomes the other major hurdle in incorporating carbon nanotubes into semiconductor devices, which could result in smaller chips with greater performance and lower power consumption.

Earlier this summer, IBM unveiled the first 7 nanometer node silicon test chip, pushing the limits of silicon technologies and ensuring further innovations for IBM Systems and the IT industry.

By advancing research of carbon nanotubes to replace traditional silicon devices, IBM is paving the way for a post-silicon future and delivering on its $3 billion chip R&D investment announced in July 2014.

IBM’s chosen design uses six nanotubes lined up in parallel to make a single transistor. Each nanotube is 1.4 nanometers wide, about 30 nanometers long, and spaced roughly eight nanometers apart from its neighbors. Both ends of the six tubes are embedded into electrodes that supply current, leaving around 10 nanometers of their lengths exposed in the middle. A third electrode runs perpendicularly underneath this portion of the tubes and switches the transistor on and off to represent digital 1s and 0s.

The IBM team has tested nanotube transistors with that design, but so far it hasn't found a way to position the nanotubes closely enough together, because existing chip technology can’t work at that scale. The favored solution is to chemically label the substrate and nanotubes with compounds that would cause them to self-assemble into position. Those compounds could then be stripped away, leaving the nanotubes arranged correctly and ready to have electrodes and other circuitry added to finish a chip.

International Conference on VLSI Design and Embeded Systems - Jan 2016

Friends, get yourself ready for the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems which will be held during January 4-8, 2016 at Kolkata, West Bengal, India.

The theme for the conference this year is "Technologies for a Safe and Inclusive World". This 5 day conference comprises: first three days (January 4 to 6, 2016) of main conference followed by Tutorials during the last two days (January 7-8, 2016).

The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on healthcare, environment, energy, transportation, and disaster management. The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of Technologies for a Safe and Inclusive World.

The Technical tracks will be grouped under the theme track and the three broad categories namely, Design Methodologies and Technology, Design Tools and EDA and Embedded System Design and Tools. The conference proceedings will be published by the IEEE Computer Society Press. Selected papers from this conference will also be published as special issues of top archival journals. 

Authors are invited to submit full-length (6 pages maximum) in IEEE CS proceedings format, original, unpublished papers with an abstract (200 words maximum) under the tracks listed below. To enable double blind review, the author list should be omitted from the main document. Papers violating length and blind-review criteria would be excluded from the review process. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered for publication. 

Track: Design Methodology and Technology 

D1: System-level Design 

ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures 

D2: Advances in Digital Design 

Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes 

D3: Analog / RF Design 

Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design 

D4: Power Aware Design 

Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools 

D5: Devices / Circuits 

New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation 

D6: Emerging Technologies 

Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing 

Track : Design Tools and EDA 

T1: Design Verification 

Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies 

T2: Test Reliability and Fault-Tolerance 

DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design 

T3: Computer-Aided Design (CAD) 

Hardware/software co-design, logic and behavioural synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction) 

Track : Embedded System Design and Tools 

E1: Embedded Systems 

Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies 

E2: FPGA Design and Reconfigurable Systems 

FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping 

E3: Wireless Systems 

Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging 

Theme Track : Technologies for a Safe and Inclusive World 

H1: Technologies for Healthcare Applications 

H2: Technologies for Smart Management of Energy Systems 

H3: Technologies for Intelligent and Secure Transportation Systems 

H4: Technologies for Safety Assurance of Embedded Circuits and Systems 

H5: Technologies for Secure Embedded Circuits and Systems 

Proposals for Tutorials and Special Sessions/Panel Discussion on the above-listed topics (but not limited to) are invited. Please check conference website for details. 

Important dates are the following: 

REGULAR PAPERS 

Abstract submission : July 19, 2015 (Sunday) 

Full Paper submission : July 26, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Camera-ready version : Oct 11, 2015 (Sunday) 

TUTORIALS 

Tutorial Proposals : July 19, 2015 (Sunday) 

Acceptance Notification : Sep 26, 2015 (Saturday) 

Presentation Slides : Nov 15, 2015 (Sunday) 

SPECIAL SESSIONS 

Proposal submission : July 19, 2015 (Sunday) 

General Chairs 

Pradip Bose, IBM 

Susmita Sur-Kolay, ISI 

Vice-General Chairs 

Indranil Sengupta, IITKGP 

Parthasarathi Dasgupta, IIMC 

Program Chairs 

Krishnendu Chakrabarty, Duke 

Pallab Dasgupta, IITKGP 

Partha P. Das, IITKGP 

Tutorial Chairs 

Hafizur Rahaman, IIEST 

Prabhat Mishra, UF 

Annajirao Garimella, Intel 

Publiciy chairs 

Chandan Giri, IIESTS 

Ken Stevens, U. Utah 

Monica Pereira, UFRN 

Robert Wille, U. Bremen 

Swarup Bhunia, CWRU 

T. -Y. Ho, NCKU

SVEditor - A SystemVerilog Editor Eclipse Plugin

Source code editors have features specifically designed to simplify and speed up input of source code, such as syntax highlighting, indentation, autocomplete and bracket matching functionality. Variety of source code editors are available for VLDH, Verilog & SystemVerilog. We have already posted feb of them like Scriptum, and Emacs. 

You might be interested in : 

Scriptum - Free VHDL and Verilog Text Editor 

GNU Emacs - A Customizable Text Editor

SVEditor is an Eclipse-based IDE (integrated development environment) for SystemVerilog and Verilog development. It provides a colourising editor for SystemVerilog with support for source navigation, content assist, source indent and auto-indent, SystemVerilog source templates and context-sensitive viewing of source documentation. Users have praised SVEditor for some of its features, such as searching for a colourisation of SystemVerilog keywords or words in a directory, auto-completion and some content assist. We believe that you can use SVEditor for debugging if you love emacs. Quoting from sourceforge.net, one user has said, “I’m totally stoked that this project is under active development. The tool is already very useful.

SVEditor provides a variety of features to make developing designs and testbench environments in SystemVerilog simpler and more efficient.

Features at a glance

The application uses a scanner that is similar to ctags for extracting the information from SystemVerilog and Verilog source files. It is engineered to be tolerant of errors, as well as to ignore unrecognized language constructs.

Among some of SVEditor’s features, we can mention colorizing for SystemVerilog keywords, outline view linked with editor, file structure view, SystemVerilog source index, syntax coloring editor, content assist, and cross-linking between data structure usage and declaration.

There are multiple ways to install the SVEditor software on your GNU/Linux computer, considering the fact that we’ve already installed the latest JRE (Java Runtime Environment) and Eclipse IDE software.

For exemple, you can download the latest version of the project as a JAR archive that can be opened into an existing Eclipse environment, you can search the application in the main software repositories of your GNU/Linux distribution, or compile it yourself using the source package provided right here on Softpedia.

For more details, do not hesitate to check out the project’s website.

Supported operating systems:

Taking a look under the hood of the SVEditor application, we can notice that it has been written entirely in the Java programming language and integrates with the Eclipse IDE for its graphical user interface.

If you don't have Eclipse IDE installed then here is link to download page of Eclipse IDE. Download Eclipse IDE

Being written in Java, SVEditor is a cross-platform software that runs on all operating ssytems where the Java Runtime Environment and Eclipse IDE are available, including GNU/Linux, Microsoft Windows and Mac OS X. It has been successfully tested on computers supporting either of the 64-bit (x86_64) or 32-bit (x86) CPU architectures.